Memory Hierarchy

Why are L1 caches often virtually indexed and physically tagged (VIPT)?

  1. APhysical addresses are not needed, so the TLB can be omitted
  2. BHits are judged only by virtual addresses, so the cache can be flushed on every process switch
  3. CThe cache set can be read in parallel while the TLB translates the address
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Answer: C. The cache set can be read in parallel while the TLB translates the address

A VIPT cache selects the set with page-offset bits that need no translation, so reading the set can start at the same time as the TLB produces the physical address. The final comparison uses the physical tag, so different processes using the same virtual address are not confused. The TLB is required to obtain the physical tag and cannot be omitted. Needing to flush the cache on every process switch is a drawback of virtually tagged designs.

  • A. The TLB is needed to compare physical tags.
  • B. Flushing on every switch is a drawback of virtually tagged caches.
  • C. Correct. Translation and set lookup proceed in parallel.
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More Memory Hierarchy questions

  1. With a cache hit time of 2 cycles, a miss rate of 4% and a miss penalty of 150 cycles, what is the average memory access time in cycles?
  2. A processor has an average CPI of 1.0 with a perfect cache. Each instruction makes 1.3 memory accesses on average, with a 2% miss rate and a 100-cycle miss penalty. What is the actual average CPI?
  3. What is the main advantage of a non-blocking cache, which accepts other accesses while a miss is being serviced?
  4. If the L1 miss rate (as a fraction of all accesses) is 4% and the L2 global miss rate (the fraction of all accesses that also miss in L2) is 1%, what is the L2 local miss rate?
  5. With 64 TLB entries and a 4 KB page size, how much memory can be accessed without TLB misses (the TLB reach)?