Memory Hierarchy

In a system with 4 KB pages and 64-byte lines, an L1 cache is to be virtually indexed and physically tagged (VIPT) with the index and offset taken only from page-offset bits. If it is 8-way set-associative, what is its maximum capacity?

  1. A32 KB
  2. B4 KB
  3. C256 KB
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Answer: A. 32 KB

Addresses within a 4 KB = 2¹² page use 12 bits, which are identical in virtual and physical addresses. Keeping index plus offset within 12 bits limits each way to 2¹² = 4 KB. With 8 ways, the cache can be up to 4 KB × 8 = 32 KB. 4 KB gives only the capacity of one way. At 256 KB the index would include page-number bits, letting the same physical address land in different sets.

  • A. Correct. 4 KB per way × 8 ways = 32 KB.
  • B. 4 KB is the capacity of a single way.
  • C. At 256 KB the index no longer fits within the page offset.
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More Memory Hierarchy questions

  1. Why are L1 caches often virtually indexed and physically tagged (VIPT)?
  2. With a cache hit time of 2 cycles, a miss rate of 4% and a miss penalty of 150 cycles, what is the average memory access time in cycles?
  3. A processor has an average CPI of 1.0 with a perfect cache. Each instruction makes 1.3 memory accesses on average, with a 2% miss rate and a 100-cycle miss penalty. What is the actual average CPI?
  4. What is the main advantage of a non-blocking cache, which accepts other accesses while a miss is being serviced?
  5. If the L1 miss rate (as a fraction of all accesses) is 4% and the L2 global miss rate (the fraction of all accesses that also miss in L2) is 1%, what is the L2 local miss rate?