Memory Hierarchy

A processor has an average CPI of 1.0 with a perfect cache. Each instruction makes 1.3 memory accesses on average, with a 2% miss rate and a 100-cycle miss penalty. What is the actual average CPI?

  1. A3.0
  2. B3.6
  3. C1.3
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Answer: B. 3.6

Memory stall cycles per instruction are 1.3 accesses × 0.02 × 100 cycles = 2.6 cycles. Adding them to the ideal CPI gives 1.0 + 2.6 = 3.6, so performance falls to 1/3.6 of ideal. 3.0 wrongly assumes one access per instruction (1.0 + 1 × 0.02 × 100). 1.3 is the number of accesses per instruction, not the CPI. Even a small miss rate badly hurts performance when the miss penalty is large.

  • A. 3.0 wrongly assumes one access per instruction.
  • B. Correct. 1.0 + 1.3 × 0.02 × 100 = 3.6.
  • C. 1.3 is the number of accesses per instruction.
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More Memory Hierarchy questions

  1. What is the main advantage of a non-blocking cache, which accepts other accesses while a miss is being serviced?
  2. If the L1 miss rate (as a fraction of all accesses) is 4% and the L2 global miss rate (the fraction of all accesses that also miss in L2) is 1%, what is the L2 local miss rate?
  3. With 64 TLB entries and a 4 KB page size, how much memory can be accessed without TLB misses (the TLB reach)?
  4. Which pair correctly states the main advantage and drawback of using large pages (huge pages)?
  5. When each row of a 2D array is 4,096 bytes (a power of two), walking down a column can cause many misses even though the cache has spare capacity. Which countermeasure is effective?