Power semiconductors

Why is a negative gate voltage (for example, −3 to −5 V) sometimes applied to SiC MOSFETs or IGBTs in the off state?

  1. ATo raise the switching frequency
  2. BTo prevent the gate voltage from being pushed up by voltage changes from the opposite switch, which could turn the device on unintentionally
  3. CTo lower the on-resistance
Show answer and explanation

Answer: B. To prevent the gate voltage from being pushed up by voltage changes from the opposite switch, which could turn the device on unintentionally

In bridge circuits, the sudden voltage change (dv/dt) when the opposite switch turns on can push up the gate voltage of the off device through its Miller capacitance. If it exceeds the threshold, the device may turn on unintentionally and cause a shoot-through, so a negative gate voltage is applied in the off state to secure margin.

  • A. It is not meant to raise the switching frequency.
  • B. Correct. It prevents false (parasitic) turn-on.
  • C. On-resistance is set by the positive gate voltage and is not lowered by negative bias.
Practice this topic Back to topic

More Power semiconductors questions

  1. What maximum junction temperature (Tj max) is commonly specified for typical silicon power devices?
  2. When choosing power devices, why are devices with a voltage rating higher than the actual operating voltage used (derating)?
  3. When does the avalanche ruggedness of a power MOSFET become important?
  4. What is a typical failure seen in power cycling tests, which repeatedly heat and cool power modules?
  5. In packages for fast-switching power devices, what is the purpose of a dedicated source terminal for the gate-drive return (Kelvin source)?