Memory Hierarchy

What is the main advantage of splitting the L1 cache into an instruction cache (I-cache) and a data cache (D-cache)?

  1. AInstructions and data no longer collide even at the same address, so capacity seems doubled
  2. BInstruction fetch and data reads or writes can proceed in parallel in the same clock cycle
  3. CSince instructions are not modified, the D-cache can be eliminated
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Answer: B. Instruction fetch and data reads or writes can proceed in parallel in the same clock cycle

In a pipeline, an instruction is fetched every cycle while another instruction reads or writes data. Splitting L1 into instruction and data caches lets these two accesses proceed in parallel without contending for a single cache port, and each can be organized to suit its own behavior. Capacity is not doubled; the total is divided between them. Data accesses are always needed, so the D-cache cannot be dropped. L2 and beyond are usually unified.

  • A. The total capacity is merely divided; it is not doubled.
  • B. Correct. Instruction fetch and data access can proceed in parallel.
  • C. Data accesses are required, so the D-cache cannot be eliminated.
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More Memory Hierarchy questions

  1. In a system with 4 KB pages and 64-byte lines, an L1 cache is to be virtually indexed and physically tagged (VIPT) with the index and offset taken only from page-offset bits. If it is 8-way set-associative, what is its maximum capacity?
  2. Why are L1 caches often virtually indexed and physically tagged (VIPT)?
  3. With a cache hit time of 2 cycles, a miss rate of 4% and a miss penalty of 150 cycles, what is the average memory access time in cycles?
  4. A processor has an average CPI of 1.0 with a perfect cache. Each instruction makes 1.3 memory accesses on average, with a 2% miss rate and a 100-cycle miss penalty. What is the actual average CPI?
  5. What is the main advantage of a non-blocking cache, which accepts other accesses while a miss is being serviced?