Logic circuits
When adding two's complement numbers, which condition indicates that an overflow has occurred?
- AWhen the carry into the most significant bit differs from the carry out of the most significant bit
- BWhen the result is 0
- CWhen the sum of the least significant bits is 1
Show answer and explanation
Answer: A. When the carry into the most significant bit differs from the carry out of the most significant bit
In two's complement addition, overflow occurs when adding two positive numbers gives a negative result or adding two negative numbers gives a positive result. This can be detected when the carry into the most significant bit differs from the carry out of it (their XOR is 1).
- A. Correct. Overflow is when the carries into and out of the MSB differ.
- B. A result of 0 does not indicate overflow.
- C. The least significant bit is irrelevant to overflow detection.