Logic circuits

What does a JK flip-flop do when a clock edge arrives with J = 1 and K = 1?

  1. AThe output inverts (toggles)
  2. BThe output is reset to 0
  3. CThe output is held
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Answer: A. The output inverts (toggles)

A JK flip-flop sets with J = 1, K = 0; resets with J = 0, K = 1; holds with J = K = 0; and toggles its output with J = K = 1. It gives meaning (toggling) to the input combination that is forbidden in an SR flip-flop.

  • A. Correct. With J = K = 1 the output toggles.
  • B. Reset occurs with J = 0, K = 1.
  • C. Hold occurs with J = K = 0.
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