Memory Hierarchy

If the cache hit rate is 95%, what is the miss rate?

  1. A95%
  2. B0.95%
  3. C5%
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Answer: C. 5%

Every access is either a hit or a miss, so miss rate = 1 − hit rate = 100% − 95% = 5%. A small-looking miss rate still matters a lot when the miss penalty is large: with a 1-cycle hit time and a 100-cycle penalty, the average is 1 + 0.05 × 100 = 6 cycles, shrinking to 2 cycles at a 99% hit rate. 95% is the hit rate itself, and 0.95% confuses a fraction with a percentage.

  • A. 95% is the hit rate itself.
  • B. 0.95% confuses a fraction with a percentage.
  • C. Correct. 100% − 95% = 5%.
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More Memory Hierarchy questions

  1. Which technique, when fetching a missed line from memory, sends the word the CPU needs first and the rest afterward?
  2. Why does fusing the two loops above into one (loop fusion) tend to be faster when N is large?
  3. Which pair gives the reason a large matrix transpose (b[j][i] = a[i][j]) tends to cause many cache misses, and a typical countermeasure?
  4. In a typical computer's memory hierarchy, which property holds more strongly for upper levels (closer to the CPU)?
  5. Why must cache designs be compared by average memory access time rather than miss rate alone?