Memory Hierarchy

What is the role of the valid bit attached to each cache line?

  1. AIt shows whether the line has been modified
  2. BIt shows the order in which the line will be evicted
  3. CIt shows if real data is present
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Answer: C. It shows if real data is present

Right after power-up or after a line is invalidated, cache contents are meaningless. A line whose valid bit is 0 is not counted as a hit even if its tag happens to match; the bit is set to 1 when correct data is loaded. This prevents empty lines from being mistaken for hits. Modification is shown by the dirty bit used in write-back caches, and eviction order is tracked by replacement information such as LRU state.

  • A. Modification is shown by the dirty bit.
  • B. Eviction order is separate replacement-policy information.
  • C. Correct. It shows whether real data is present, preventing false hits on empty lines.
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More Memory Hierarchy questions

  1. What is the main effect of a victim cache, a small fully associative buffer that temporarily holds lines evicted from the L1 cache?
  2. In a multilevel cache with an L2 below the L1, what is the L2's main role?
  3. Which describes an inclusive cache, where a lower level (such as L2) contains everything in the upper level (L1)?
  4. What changes when a cache is switched from direct-mapped to set-associative?
  5. In an 8-way set-associative cache, how many tags are compared in parallel on each access?