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How to read datasheets

The transmitting IC has a clock-to-output delay of max 6 ns, the board trace delay is 1 ns, and the receiving IC has a setup time of 3 ns. Ignoring clock skew, what is the maximum usable clock frequency?

  1. A100 MHz
  2. BAbout 143 MHz
  3. C250 MHz
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Answer: A. 100 MHz

The slowest time for data to reach the receiver is 6 + 1 = 7 ns. At the receiver, the data must be valid 3 ns before the next clock edge, so the clock period must be at least 7 + 3 = 10 ns, giving a maximum frequency of 1/10 ns = 100 MHz. The key point in checking setup is to use the maximum (max) delay. About 143 MHz is the value obtained by forgetting to add the setup time (1/7 ns). In real designs, margin for clock skew and jitter is also subtracted.

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