FSI vs BSI vs Stacked Image Sensors: Key Differences
CMOS image sensors fall into three structures depending on which side light enters from and where the circuits are placed. Front-side illumination (FSI) brings light in through the front surface, where the wiring layers are, so part of the light is blocked by the wiring. Back-side illumination (BSI) flips the wafer, thins it to a few µm and brings light in through the back, which has no wiring, so even small pixels keep their sensitivity. A stacked sensor bonds a BSI pixel chip to a logic chip that carries the readout and image-processing circuits, making the chip smaller and the readout faster.
| Aspect | Front-side illumination (FSI) | Back-side illumination (BSI) | Stacked |
|---|---|---|---|
| Side where light enters | The front side, where the wiring layers are. Light passes through microlenses, color filters and gaps between several wiring layers to reach the photodiode | The side opposite the wiring layers (back side). Light reaches the photodiode without passing through wiring | Back side. The pixel chip has a BSI structure |
| Basic structure | Pixels and peripheral circuits are made on a single silicon substrate | After front-side processing, the wafer is bonded to a support wafer and the original substrate is thinned to a few µm | A pixel wafer is bonded to a logic wafer that performs readout, AD conversion and image processing. The logic wafer replaces the support wafer |
| Fill factor and sensitivity | Wiring blocks part of the light, and sensitivity tends to drop as pixels get smaller | Almost the entire pixel area can receive light, so sensitivity is high | Same as BSI |
| Light at oblique angles | The layers that light passes through are thick, so oblique light is easily lost | The optical path is short, so it handles oblique light well | Same as BSI |
| Wiring flexibility | Wiring must be kept out of the light path, which limits the number of layers and layout | No optical constraints, so more wiring layers can be used | Much of the circuitry can be moved to the logic chip |
| Location of peripheral circuits | Around the pixel array, made in the same process as the pixels | Around the pixel array, made in the same process as the pixels | On the logic chip under the pixels, which can use a finer process suited to logic. Some three-layer designs add a memory chip |
| Chip area | Larger than the pixel area by the amount of peripheral circuitry | Larger than the pixel area by the amount of peripheral circuitry | Can be smaller, because circuits sit under the pixels |
| Readout speed and features | Standard | Standard | Easy to add more circuitry, so high-speed readout, high frame rates and processing such as HDR are easier to include |
| Manufacturing difficulty | Simplest and cheapest | Requires bonding, thinning and back-surface treatment (passivation) | In addition to the BSI steps, requires wafer-to-wafer bonding and electrical connections (TSVs or Cu-Cu hybrid bonding), so it is the most complex |
| Main challenges | There is a limit to pixel shrinking | Dark current from back-surface defects, crosstalk to neighboring pixels in thin silicon (suppressed with DTI), and lower sensitivity in red and near-infrared | In addition to the BSI challenges, bonding yield and the effect of heat from the logic on dark current and noise |
| Typical uses | Industrial and low-cost sensors with large pixels | Sensors that need sensitivity with small pixels, such as in smartphones and digital cameras | Sensors that need speed and small size, such as high-end smartphones, high-speed cameras and automotive |
Figures are typical orders of magnitude and vary by process generation and product.