Multicore & Synchronization

The two threads above run simultaneously on different cores (assume no compiler reordering). Which outcome cannot occur under sequential consistency but can occur on real CPUs such as x86?

// Initially x = 0, y = 0
// Thread 1        // Thread 2
x = 1;            y = 1;
r1 = y;           r2 = x;
  1. Ar1 = 1 and r2 = 1
  2. Br1 = 0 and r2 = 1
  3. Cr1 = 0 and r2 = 0
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Answer: C. r1 = 0 and r2 = 0

Under sequential consistency one of the writes happens first, so at least one read must see 1. On real CPUs, however, x = 1 first enters the core's store buffer, and before it becomes visible to other cores the later read r1 = y can fetch its value from cache or memory. If both cores do this, both read 0. A memory barrier between the write and the read prevents it.

  • A. This occurs under sequential consistency if both writes finish first.
  • B. This occurs under sequential consistency if thread 1 finishes first.
  • C. Correct. Reads proceed while the writes sit in store buffers.
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More Multicore & Synchronization questions

  1. What is a characteristic of the x86 memory consistency model (TSO, total store order)?
  2. Which statement is correct about weak memory consistency models such as those of Arm and RISC-V (RVWMO)?
  3. What is the role of a memory barrier (fence) instruction?
  4. In the code above, thread 1 prepares data and then signals with flag, and thread 2 waits for flag and then reads data. On a CPU with a weak memory model, what is needed for thread 2 to reliably read 42?
  5. Which statement is correct about memory operations with acquire and release semantics?