Multicore & Synchronization

What is the role of a memory barrier (fence) instruction?

  1. AIt guarantees that memory operations before the barrier become visible to other cores before those after it
  2. BIt physically partitions memory and forbids access
  3. CIt stops the program until every thread arrives
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Answer: A. It guarantees that memory operations before the barrier become visible to other cores before those after it

CPUs can reorder memory operations, so passing data to other cores in a fixed order requires an instruction that prevents it. A memory barrier makes all earlier reads and writes complete (become visible to other cores) before later ones are performed. Lock acquisition and release include this barrier effect, which is why variables protected by a lock are passed correctly.

  • A. Correct. It stops memory operations from being reordered across it.
  • B. Forbidding access is done by page protection and similar.
  • C. That is barrier synchronization among threads.
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More Multicore & Synchronization questions

  1. In the code above, thread 1 prepares data and then signals with flag, and thread 2 waits for flag and then reads data. On a CPU with a weak memory model, what is needed for thread 2 to reliably read 42?
  2. Which statement is correct about memory operations with acquire and release semantics?
  3. In C, why is marking a flag variable shared between threads volatile not sufficient for synchronization?
  4. Why do C11 _Atomic and C++11 std::atomic let programmers specify a memory order?
  5. Which correctly compares coarse-grained locking (one lock for a whole large data structure) with fine-grained locking (separate locks for each part)?