Multicore & Synchronization

Which describes an atomic instruction?

  1. AAn instruction that performs a memory read and write as a single operation that no other core can interrupt partway
  2. BAn instruction for physics calculations that counts atoms
  3. CThe fastest instruction, always finishing in one clock
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Answer: A. An instruction that performs a memory read and write as a single operation that no other core can interrupt partway

An atomic instruction performs a read, compute and write sequence such that no other core's access can come in between. Other cores see only the state before or after the operation. Examples include CAS (compare-and-swap), fetch-and-add and RISC-V's LR/SC and AMO instructions, which are the building blocks of locks and lock-free data structures.

  • A. Correct. To other cores it appears to happen instantaneously.
  • B. Atomic here means indivisible.
  • C. Its defining feature is indivisibility, not speed.
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More Multicore & Synchronization questions

  1. What does the atomic CAS (compare-and-swap) instruction do?
  2. The code above doubles the shared variable counter using CAS(&p, expected, new). When does the CAS fail so the loop repeats?
  3. With an instruction pair such as RISC-V LR/SC (load-reserved / store-conditional), when does the SC fail?
  4. Which describes the ABA problem that affects lock-free data structures built with CAS?
  5. What does a fetch-and-add instruction, such as RISC-V amoadd.w or x86 lock xadd, do?