Multicore & Synchronization

With an instruction pair such as RISC-V LR/SC (load-reserved / store-conditional), when does the SC fail?

  1. AWhen the value SC writes equals the value LR read
  2. BWhen the reservation is lost, for example because another core wrote that address between the LR and the SC
  3. CWhenever any other instruction is executed between LR and SC
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Answer: B. When the reservation is lost, for example because another core wrote that address between the LR and the SC

LR reads a value and at the same time "reserves" the address. When SC later writes, it succeeds if the reservation is intact and fails without writing if the reservation was lost, for example because another core wrote there. Whereas CAS checks for a matching value, LR/SC checks whether any write happened, so it also detects a value that changed and changed back. Arm has a similar instruction pair.

  • A. Writing the same value still succeeds.
  • B. Correct. It checks whether a write occurred, not the value.
  • C. A short sequence of instructions may come in between.
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More Multicore & Synchronization questions

  1. Which describes the ABA problem that affects lock-free data structures built with CAS?
  2. What does a fetch-and-add instruction, such as RISC-V amoadd.w or x86 lock xadd, do?
  3. Which describes a spinlock?
  4. In which situation is a spinlock least suitable?
  5. Why does a spinlock usually wait with ordinary reads and use an atomic instruction only when the lock looks free (test-and-test-and-set), instead of retrying the atomic write directly?