Memory Hierarchy

Roughly how many times longer is a main-memory DRAM access than an L1 cache hit (for typical PC or server CPUs)?

  1. A2 to 3 times
  2. BTens to about a hundred times
  3. CMore than 100,000 times
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Answer: B. Tens to about a hundred times

An L1 hit takes a few cycles (around 1 ns), while a DRAM access takes tens to about 100 ns, a difference of tens to a hundred times. For a CPU running at several GHz that means waiting hundreds of cycles, which is why cache hierarchies and prefetching are essential to performance. If the gap were only 2 to 3 times, caches would matter far less. More than 100,000 times is closer to the gap with SSDs or hard disks, not DRAM.

  • A. The gap is far larger than 2 to 3 times.
  • B. Correct. Tens to a hundred times, equal to hundreds of CPU cycles.
  • C. More than 100,000 times is closer to the gap with storage.
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More Memory Hierarchy questions

  1. What is the role of the valid bit attached to each cache line?
  2. What is the main effect of a victim cache, a small fully associative buffer that temporarily holds lines evicted from the L1 cache?
  3. In a multilevel cache with an L2 below the L1, what is the L2's main role?
  4. Which describes an inclusive cache, where a lower level (such as L2) contains everything in the upper level (L1)?
  5. What changes when a cache is switched from direct-mapped to set-associative?