Memory Hierarchy

Which misses are not reduced even by making a cache fully associative?

  1. AMisses caused by two blocks competing for the same set and repeatedly evicting each other
  2. BMisses caused by the data used exceeding the cache capacity
  3. CMisses caused by uneven placement in a direct-mapped layout
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Answer: B. Misses caused by the data used exceeding the cache capacity

In a fully associative cache any data can go anywhere, so conflict misses from competing for a set disappear. But if the data a program repeatedly uses (its working set) is larger than the whole cache, it cannot fit wherever it is placed, and evictions occur. These are capacity misses, which require a larger cache or a smaller reuse footprint through techniques such as loop blocking. Uneven placement and set competition both cause conflict misses.

  • A. Set competition causes conflict misses, which full associativity eliminates.
  • B. Correct. Capacity misses from an overflowing working set remain.
  • C. Misses from uneven placement are also conflict misses.
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More Memory Hierarchy questions

  1. What is the effect of increasing a cache's line size?
  2. What is the main purpose of a write buffer in a write-through cache?
  3. In a write-back cache, what is the role of the dirty bit attached to each line?
  4. Which policy, on a write miss, writes directly to the lower level without loading the line into the cache?
  5. A fully associative cache holding 2 lines with LRU replacement starts empty. If blocks are referenced in the order A, B, A, C, B, A, how many misses occur?