Multicore & Synchronization

What is a characteristic of the x86 memory consistency model (TSO, total store order)?

  1. AIt is the weakest model, allowing every combination of reordering
  2. BIt is exactly sequential consistency, allowing no reordering at all
  3. CIt is a relatively strong model that allows only a later read of a different address to appear before an earlier write
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Answer: C. It is a relatively strong model that allows only a later read of a different address to appear before an earlier write

Under TSO, writes stay ordered with writes, reads with reads, and a write after a read stays ordered; only a read of a different address may overtake an earlier write. This model directly reflects the presence of a store buffer. Many programs behave intuitively within these limits, so barriers are needed relatively rarely on x86.

  • A. That is closer to weak models such as Arm or RISC-V.
  • B. Write-then-read reordering does occur.
  • C. Correct. Only the reordering caused by the store buffer is visible.
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More Multicore & Synchronization questions

  1. Which statement is correct about weak memory consistency models such as those of Arm and RISC-V (RVWMO)?
  2. What is the role of a memory barrier (fence) instruction?
  3. In the code above, thread 1 prepares data and then signals with flag, and thread 2 waits for flag and then reads data. On a CPU with a weak memory model, what is needed for thread 2 to reliably read 42?
  4. Which statement is correct about memory operations with acquire and release semantics?
  5. In C, why is marking a flag variable shared between threads volatile not sufficient for synchronization?