Multicore & Synchronization

What does a memory consistency model define?

  1. AThe cache line size and the number of sets
  2. BThe kind of transistors used in main-memory DRAM
  3. CIn what order a core's reads and writes to multiple addresses may be observed by other cores
Show answer and explanation

Answer: C. In what order a core's reads and writes to multiple addresses may be observed by other cores

For performance, CPUs may reorder memory operations, for example by holding writes in a store buffer or performing reads early. They are designed so that results within one core are unchanged, but other cores may observe the operations in a different order. A memory consistency model defines which reorderings can occur and is the contract that lets programmers write correct synchronization.

  • A. That is cache organization.
  • B. It has nothing to do with circuit technology.
  • C. Correct. It is a contract between hardware and programmers.
Practice this topic Back to topic

More Multicore & Synchronization questions

  1. Which describes sequential consistency?
  2. The two threads above run simultaneously on different cores (assume no compiler reordering). Which outcome cannot occur under sequential consistency but can occur on real CPUs such as x86?
  3. What is a characteristic of the x86 memory consistency model (TSO, total store order)?
  4. Which statement is correct about weak memory consistency models such as those of Arm and RISC-V (RVWMO)?
  5. What is the role of a memory barrier (fence) instruction?