Multicore & Synchronization

Which statement is correct about weak memory consistency models such as those of Arm and RISC-V (RVWMO)?

  1. AThey allow many reorderings of accesses to different addresses, and programs insert barriers where order is needed
  2. BThey allow no reordering, so barrier instructions do not exist
  3. CThey do not even guarantee ordering of accesses to the same address
Show answer and explanation

Answer: A. They allow many reorderings of accesses to different addresses, and programs insert barriers where order is needed

Weak models let hardware reorder fairly freely reads and writes to different addresses that have no dependence. This simplifies circuits and helps performance and power efficiency, but when passing data to other cores, order must be stated explicitly with fence instructions or with loads and stores carrying acquire or release semantics. In high-level languages, using atomic variables makes the compiler emit the right instructions.

  • A. Correct. Hardware gains freedom, and ordering is requested explicitly.
  • B. RISC-V has the fence instruction.
  • C. Ordering to the same address is maintained by coherence.
Practice this topic Back to topic

More Multicore & Synchronization questions

  1. What is the role of a memory barrier (fence) instruction?
  2. In the code above, thread 1 prepares data and then signals with flag, and thread 2 waits for flag and then reads data. On a CPU with a weak memory model, what is needed for thread 2 to reliably read 42?
  3. Which statement is correct about memory operations with acquire and release semantics?
  4. In C, why is marking a flag variable shared between threads volatile not sufficient for synchronization?
  5. Why do C11 _Atomic and C++11 std::atomic let programmers specify a memory order?