Memory Hierarchy

What generally happens to hit time as cache capacity increases, and why?

  1. AIt shortens, because more data inside means less time searching
  2. BIt stays the same, because hit time depends only on line size
  3. CIt tends to lengthen, as wiring and selection logic grow
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Answer: C. It tends to lengthen, as wiring and selection logic grow

A larger cache lowers the miss rate, but the memory array grows, wires lengthen, and the index decoding and output selection circuits get bigger, so hit time tends to increase. That is why L1 is kept small, around tens of KB, while large capacity is provided by L2 and L3 in a multilevel hierarchy. Hit time does not shorten, nor does it depend on line size alone. Capacity is set by balancing miss rate against hit time.

  • A. Making it larger does not shorten the search; it lengthens it.
  • B. Hit time also depends on capacity and associativity.
  • C. Correct. Larger wiring and selection circuits tend to lengthen hit time.
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More Memory Hierarchy questions

  1. Why does traversing the linked list above tend to be much slower than reading an array with the same number of elements in order?
  2. Each miss fetches a 64-byte line and memory latency is 100 ns. With only one miss outstanding at a time, read bandwidth is about 0.64 GB/s. If 10 misses can be outstanding at once, what is the bandwidth approximately (assuming no other limits)?
  3. When writing out a large amount of data that will not be read back for a while, what is the main benefit of non-temporal stores that bypass the cache?
  4. If the cache hit rate is 95%, what is the miss rate?
  5. Which technique, when fetching a missed line from memory, sends the word the CPU needs first and the rest afterward?