Memory Hierarchy

In a write-back cache, what is the role of the dirty bit attached to each line?

  1. AIt shows whether the line's data is valid and can be read
  2. BIt shows the line was modified and differs from memory
  3. CIt shows the time the line was last accessed
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Answer: B. It shows the line was modified and differs from memory

A write-back cache completes writes in the cache alone, so some lines end up newer than main memory. The dirty bit marks such modified lines so that only dirty lines need to be written back on eviction; clean lines can simply be discarded, avoiding wasted writes. Validity is indicated by the valid bit, and access order is tracked by separate replacement information such as LRU state.

  • A. Validity is indicated by the valid bit.
  • B. Correct. It marks the line as modified, deciding whether it is written back on eviction.
  • C. Access order is separate information used by the replacement policy.
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More Memory Hierarchy questions

  1. Which policy, on a write miss, writes directly to the lower level without loading the line into the cache?
  2. A fully associative cache holding 2 lines with LRU replacement starts empty. If blocks are referenced in the order A, B, A, C, B, A, how many misses occur?
  3. For which access pattern is hardware prefetching especially effective?
  4. When inserting software prefetch instructions, which statement about how far ahead to fetch (the prefetch distance) is correct?
  5. In the loop above, an int is 4 bytes, a cache line is 64 bytes, and the array is not cached and starts on a line boundary. Without prefetching, what is the miss rate for reading the array?