Silicon photonics

Why is active alignment—aligning while actually passing laser light through and measuring the output—often used when attaching single-mode fiber to a silicon photonic chip?

  1. AThe fiber core is thick, 50 µm or more in diameter, and aligning by eye using the outline makes the light so strong that it damages the photodetector
  2. BFixing the fiber while passing light through matches the refractive indices of the fiber and chip, so no loss arises even if the position shifts
  3. CThe mode is small, so even a misalignment of a few µm or less greatly increases loss, and the optimal position must be found by measurement
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Answer: C. The mode is small, so even a misalignment of a few µm or less greatly increases loss, and the optimal position must be found by measurement

Single-mode fiber has a mode diameter of about 10 µm, and even between modes of the same size, a lateral offset of about 2.5 µm adds about 1 dB of loss. At couplers where the chip-side mode is smaller, the allowable misalignment is submicron. Aligning by the outline alone (passive alignment) is often not accurate enough, so light is passed through, the position that maximizes received power is searched for, and the fiber is fixed with UV-curable resin or similar. However, this takes time for each fiber and is a major contributor to manufacturing cost, so passive alignment methods that align simply by seating the fiber in V-grooves or the like are also being researched and commercialized.

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More Silicon photonics questions

  1. What is the main reason silicon photonics is said to be well suited to mass production in semiconductor fabs?
  2. Which is considered one of the main causes of propagation loss (dB/cm) in silicon waveguides?
  3. Which correctly describes the cutback method for measuring the propagation loss of silicon waveguides?
  4. In CPO, which integrates optical components with a switch IC and others in one package, why is it especially important to test optical characteristics at the wafer level before assembly?
  5. Why is a configuration used in which the chip with optical devices (PIC) and the chip with electronic circuits such as drivers and TIAs (EIC) are fabricated separately and then stacked and connected?