Hardware Security

Why are debug ports such as JTAG disabled or placed behind authentication in shipped products?

  1. ADebug ports drain the battery by increasing power
  2. BDebug ports break automatically after shipping
  3. CDebug ports allow reading and writing memory and registers and halting programs, so left open they let firmware and keys be stolen or altered
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Answer: C. Debug ports allow reading and writing memory and registers and halting programs, so left open they let firmware and keys be stolen or altered

Debug ports such as JTAG and SWD are powerful tools for freely inspecting a chip during development. Left active in a product, an attacker can connect equipment to the board's pins and read out firmware, bypass secure boot or extract keys. Countermeasures include disabling them with eFuses at shipping or enabling them only after cryptographic authentication.

  • A. Power is not the main reason.
  • B. They do not break automatically.
  • C. Correct. What helps development also helps attackers.
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More Hardware Security questions

  1. Which describes the tamper resistance required of security chips such as smart cards?
  2. Which method is commonly used to store keys written into a chip?
  3. Besides speed, what advantage comes from giving CPUs dedicated AES instructions (such as AES-NI)?
  4. What must be observed when implementing cryptographic code in constant time?
  5. What is the idea of partitioning a shared cache as a countermeasure to cache side channels?