How to read datasheets
Which correctly describes the problem with connecting the output of an IC powered from 3.3 V directly to a CMOS input powered from 5 V (VIH(min) = 0.7 × VDD)?
- AVIH(min) becomes 3.5 V, so a 3.3 V high level cannot be reliably recognized as H
- BA 3.3 V signal is an overvoltage for the 5 V side's input, so the input pin will be damaged
- CThe high level exceeds 2.5 V, half the supply voltage, so they can be connected without problems
Show answer and explanation
Answer: A. VIH(min) becomes 3.5 V, so a 3.3 V high level cannot be reliably recognized as H
For a 5 V CMOS input with VIH(min) = 0.7 × VDD, VIH(min) is 3.5 V. The high level of the 3.3 V side's output is at most about 3.3 V, so it does not reach VIH(min) and is not guaranteed to be recognized as H. Remedies include using an IC with TTL-compatible inputs, whose VIH(min) is 2.0 V, or inserting a level-shifter IC. Applying a signal lower than the supply voltage does not in itself damage the input; the problem is that the logic levels do not match.