Ripple-Carry vs Carry-Lookahead vs Carry-Save Adder: Delay, Area

All three are adders built from full adders, but they handle carries differently. A ripple-carry adder chains full adders so the carry passes from the lowest bit to the highest in turn, and the delay grows in proportion to the bit width n (O(n)). A carry-lookahead adder computes all carries in parallel from per-bit generate and propagate signals, and with a hierarchical lookahead the delay grows only as O(log n). A carry-save adder reduces three numbers to two, a sum word and a carry word, without propagating carries, so its delay is one full-adder delay regardless of width. Multipliers reduce partial products with trees of carry-save adders (such as Wallace trees) and add the final two numbers with a fast adder.

AspectRipple-carry adderCarry-lookahead adderCarry-save adder
Inputs and outputsAdds two numbers (and a carry-in) into one sum and a carry-outAdds two numbers (and a carry-in) into one sum and a carry-outReduces three numbers to two, a sum word S and a carry word Cy (A + B + C = S + Cy)
How the carry is handledEach full adder waits for the carry from below and passes it upward in turnUses generate g = a·b and propagate p = a ⊕ b and expands c(i+1) = g(i) + p(i)·c(i) to compute carries in parallelCarries are not passed to the neighboring bit; they go to the next stage as a word shifted one bit left
How delay growsO(n); in the worst case the carry travels from the lowest bit to the highestO(log n) (with a hierarchical lookahead)O(1); one full-adder delay regardless of width
64-bit figuresThe carry passes through 64 full addersThree levels of 4-bit blocks; in a Kogge-Stone parallel-prefix adder, the carry computation takes log₂64 = 6 stagesOne stage is one full-adder delay; a Wallace tree that reduces 64 partial products to two takes 10 stages
AreaSmallest: n full adders for n bitsLarger by the lookahead logic; faster designs use more gates and wiring (roughly n log n for Kogge-Stone)One stage is n full adders with no carry chain; a whole multiplier tree scales with the number of partial-product bits (about n²)
Result formatOrdinary binaryOrdinary binaryRedundant form split into a sum word and a carry word; an ordinary adder is needed at the end to get a single value
Typical usesSmall or low-power circuits where speed is not critical; in FPGAs, often built on dedicated carry-chain logicCPU ALUs, address calculation, floating-point units, the final addition in multipliersPartial-product reduction in multipliers (Wallace and Dadda trees), accumulation in multiply-accumulate units, adding many numbers
Related designsCarry-skip and carry-select adders (between the two in speed and area)Parallel-prefix adders (Kogge-Stone, Brent-Kung and others)4:2 compressors, combination with Booth's algorithm to reduce partial products

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Ripple-carry adder
Use it for narrow widths, or when area and power matter more than speed. Its simple, regular structure maps efficiently onto devices with dedicated fast carry paths, such as FPGAs.
Carry-lookahead adder
Use it when a single two-operand addition must finish quickly, as in CPU ALUs and adders on the critical path. The hierarchy and the choice of parallel-prefix structure trade stage count against area and wiring.
Carry-save adder
Use it when adding three or more numbers. It reduces the count without waiting for carries and does one final addition with a carry-lookahead or similar adder, so it pays off in multipliers that add many partial products and in MAC units that accumulate repeatedly.

FAQ

How big is the difference between O(n) and O(log n) in practice?

At 64 bits, the carry of a ripple-carry adder passes through 64 full adders, while a Kogge-Stone parallel-prefix adder computes carries in log₂64 = 6 stages. The delay per stage differs between circuits, so this is not a simple ratio, but the gap widens as the width grows, and a ripple-carry adder is too slow for 64-bit addition in a GHz-class processor.

How can the carry-save adder be checked with numbers?

Feed in the 4-bit values 5 (0101), 6 (0110) and 7 (0111). The word S made of each bit's sum is 0100 (4), and the word Cy made of each bit's carry shifted one bit left is 1110 (14). 4 + 14 = 18, which equals 5 + 6 + 7. Each bit is an independent full adder, so nothing waits for a carry.

How is the number of Wallace tree stages determined?

Each stage of carry-save adders turns three numbers into two, so the count shrinks to about two-thirds per stage. With h partial products, one stage leaves 2⌊h/3⌋ + (h mod 3); 8 take 4 stages, 16 take 6, 32 take 8 and 64 take 10 to reach two. The stage count grows roughly with the logarithm of the width, and adding the final two numbers with a fast adder completes the product.

Why isn't the full carry-lookahead equation used directly for wide adders?

Fully expanding the carry equations adds more terms for each higher bit and soon requires gates with too many inputs. Instead, groups of about 4 bits produce a group generate G and group propagate P, and the next level uses the same lookahead logic on them. Parallel-prefix adders generalize this idea.

Check your understanding

What is the drawback of a ripple-carry adder made by chaining full adders?

  1. AIt cannot handle negative numbers
  2. BBecause the carry propagates from the lower bits in sequence, the delay grows in proportion to the number of bits
  3. CThe circuit size does not change even as the number of bits increases
Show answer and explanation

Answer: B. Because the carry propagates from the lower bits in sequence, the delay grows in proportion to the number of bits

In a ripple-carry adder, each full adder waits for the carry from below, so the carry ripples from the least to the most significant bit and delay grows linearly with width. At 64 bits that is 64 full-adder delays, too slow for GHz CPUs. Being small and simple, it is used where speed does not matter. Faster designs use carry-lookahead, carry-select and parallel-prefix (e.g., Kogge-Stone) adders.

Why is a carry-lookahead adder fast?

  1. AIt reduces the number of bits being added
  2. BIt doubles the clock frequency
  3. CIt computes the carry for each bit in parallel from the inputs without waiting for propagation from the lower bits
Show answer and explanation

Answer: C. It computes the carry for each bit in parallel from the inputs without waiting for propagation from the lower bits

A carry-lookahead adder uses per-bit generate G = A·B (always produces a carry) and propagate P = A⊕B (passes a lower carry) to compute each carry directly from the inputs in parallel: C1 = G0 + P0·C0, C2 = G1 + P1·G0 + P1·P0·C0, and so on. Delay then grows only with the logarithm of the width. Because the expressions grow long, about 4-bit blocks are combined hierarchically.

In a carry-lookahead adder, which gives the definitions of each bit's generate signal g and propagate signal p (a and b are that bit's inputs) and the carry into the next bit, c(i+1)?

  1. Ag = a + b, p = a·b, c(i+1) = p + g·c(i)
  2. Bg = a·b, p = a ⊕ b, c(i+1) = g + p·c(i)
  3. Cg = a ⊕ b, p = a·b, c(i+1) = g·p·c(i)
Show answer and explanation

Answer: B. g = a·b, p = a ⊕ b, c(i+1) = g + p·c(i)

If a and b are both 1, a carry is produced regardless of the incoming carry, so the generate signal is g = a·b. If exactly one of them is 1, the incoming carry passes upward, so the propagate signal is p = a ⊕ b (OR is also used). Hence c(i+1) = g(i) + p(i)·c(i); expanding this lets every carry be computed in parallel with two-level logic from the g and p signals and the lowest carry alone. Formulas that swap generate and propagate do not compute correctly.

  1. Why are carry-save adders used to sum the many partial products in a multiplier?
  2. Which describes a Wallace tree used in fast multipliers?
  3. Which correctly lists the inputs of a full adder?

Practice Computer Arithmetic questions

Key terms explained

Full adder
A circuit that adds two bits plus a carry-in from the lower digit and outputs a sum and a carry-out. A version without carry-in is a half adder. Chaining full adders makes a multi-bit adder.
Carry-lookahead adder
An adder that computes carries in parallel from each bit's generate signal g = a·b and propagate signal p = a ⊕ b, without waiting for carries to ripple. Delay stays small even for wide operands.
Carry-save adder
An adder that reduces three numbers to two, a sum and a carry, without propagating carries. Made of independent full adders per bit, its delay is constant, so multipliers use it to add many partial products.
Wallace tree
A multiplier structure that reduces many partial products in parallel with a tree of carry-save adders. Its depth grows only logarithmically with width, so it is used in fast multipliers; a final adder sums the last two numbers.
Booth's algorithm
A multiplication method that recodes the multiplier's bits, for example in pairs, into signed digits to reduce the number of partial products. Radix-4 Booth encoding roughly halves them.
Critical path
The path with the largest delay in a circuit, which sets the maximum clock frequency. In STA it is the path with the smallest slack, and speeding up a design starts by reducing its delay.

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