AD/DA conversion

Which correctly describes the acquisition time of a sample-and-hold circuit?

  1. AThe time, in track mode, for the hold capacitor voltage to settle to the input within the required accuracy
  2. BHow fast the held voltage gradually decreases
  3. CThe time until the conversion result is output digitally
Show answer and explanation

Answer: A. The time, in track mode, for the hold capacitor voltage to settle to the input within the required accuracy

Acquisition time is the time needed in track mode for the hold capacitor voltage to approach the input voltage within a specified error. If it is insufficient, the previous value still affects the result and causes conversion errors.

  • A. Correct. It is the time for the capacitor voltage to catch up with the input.
  • B. The decrease in held voltage is called droop.
  • C. The time until the result is output is the conversion time or latency.
Practice this topic Back to topic

More AD/DA conversion questions

  1. What is the technique of deliberately sampling a signal centered at 70 MHz with a 10 MHz bandwidth at a lower sampling frequency, which also performs frequency conversion?
  2. What is the main purpose of deliberately adding a small noise (dither) before AD conversion?
  3. What is the effect of raising the order of the modulator in a ΔΣ AD converter (for example, from first to second order)?
  4. In a time-interleaved ADC that alternates between several ADCs, what problem is caused by mismatches in offset, gain and timing between the individual ADCs?
  5. Which correctly describes the "offset binary" code used in ADCs that handle both positive and negative voltages?