SIMD vs SIMT: Key Differences Explained
SIMD and SIMT both apply the same operation to many data elements with a single instruction, but they look different to the program. SIMD is the CPU's vector instructions: the programmer or compiler lays data out in fixed-width vector registers and uses the instructions explicitly. SIMT is the GPU's approach: you write ordinary code for a single thread, and the hardware groups threads, such as 32 of them, into a warp and runs them with the same instruction. Each thread can have its own branches, but when threads in a warp take different paths, both paths are executed one after the other, which lowers efficiency.
| Aspect | SIMD | SIMT |
|---|---|---|
| Execution model | One instruction processes multiple elements laid out in a vector register at the same time | One instruction is executed at the same time by many threads grouped into a warp. Each thread has its own registers |
| How it looks to the program | Written with the vector width in mind, using intrinsics, assembly or the compiler's auto-vectorization | The work of a single thread is written as scalar code. The hardware does the grouping |
| Parallel width | Set by the register width. Example: 512 bits holds 16 numbers of 32 bits | The warp width (such as 32 threads). The whole chip holds tens of thousands of threads at once |
| Branch handling | Per-element branches cannot be written. Both sides are computed and selected with a mask from a comparison | Can be written per thread. If threads in a warp diverge, both paths run in turn while threads not on the current path sit idle (divergence) |
| Managing active elements | The programmer or compiler specifies them explicitly with masked or blend instructions | The hardware manages active threads automatically |
| Memory access | Good at reading contiguous addresses together. Scattered addresses are handled with gather/scatter instructions, but slowly | Each thread can specify any address. When adjacent threads read adjacent addresses, the accesses are combined (coalescing) |
| Hiding memory latency | Large caches, out-of-order execution, prefetching | Switching among many warps, running other warps while some wait |
| Place in Flynn's taxonomy | SIMD itself | A form of SIMD presented in the shape of threads |
| Typical uses | CPU vector instructions. Loops for image and audio processing, cryptography, matrix operations and so on | GPU warps. Large-scale parallel computing such as graphics, AI training and inference, and scientific computing |
Figures are typical orders of magnitude and vary by process generation and product.