OS & Hardware

Why can a process context switch degrade performance more than the time spent saving and restoring registers would suggest?

  1. AThe CPU clock frequency drops on every switch
  2. BThe program is reloaded from disk on every switch
  3. CCache and TLB misses rise after the switch
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Answer: C. Cache and TLB misses rise after the switch

Saving and restoring registers is quick, but after the switch the caches and TLB hold the previous process's contents, so the new process misses until its data and translations are reloaded. On CPUs without ASIDs, the TLB must also be flushed when changing address spaces. This indirect cost can exceed the direct switching time. The clock does not slow down, and programs are not reloaded from disk.

  • A. Switching does not lower the clock frequency.
  • B. The program stays in memory and is not reloaded.
  • C. Correct. It is the indirect cost of more cache and TLB misses.
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More OS & Hardware questions

  1. What is the advantage of tagging each TLB entry with an ASID (address space identifier)?
  2. What mechanism mainly lets the OS reclaim the CPU at regular intervals, even from programs that never give it up voluntarily, and switch to other processes?
  3. When reading a device status register via memory-mapped I/O as above, why is it declared volatile and the region configured as uncached?
  4. When is polling, in which the CPU repeatedly checks device status instead of using interrupts, advantageous?
  5. In a system where hardware does not keep caches coherent, what must software do before the CPU reads data a device wrote to main memory via DMA?