Multicore & Synchronization
When 64 cores continuously update one shared counter with atomic instructions, adding cores does not speed things up. What is the main reason?
- AAtomic instructions can execute on only one core
- BWith many cores the counter value automatically gets smaller
- CThe counter's cache line moves from core to core, so updates proceed only one at a time
Show answer and explanation
Answer: C. The counter's cache line moves from core to core, so updates proceed only one at a time
An atomic update requires the core to own the line in the M state, so the line migrates to another core on every update. Each migration costs inter-core communication time, and only one core can update at a time, so adding cores just lengthens the wait. The fix is to reduce shared writes, for example by having each core count locally and summing at the end.
- A. Any core can execute them.
- B. The value does not change by itself.
- C. Correct. Contention for the line determines performance.