OS & Hardware

In virtualization with nested paging (two-stage address translation), which describes what the hardware does?

  1. AIt walks only the guest OS's page tables and does not use the hypervisor's tables
  2. BIt translates guest virtual → guest physical → host physical
  3. CThe hypervisor intercepts every memory access and translates each one in software
Show answer and explanation

Answer: B. It translates guest virtual → guest physical → host physical

A guest OS believes its physical addresses (guest physical addresses) are real memory, but the memory actually lives elsewhere as assigned by the hypervisor. With nested paging, hardware translates through the guest's page tables to a guest physical address and then through the hypervisor's tables to a host physical address. The hypervisor no longer needs to intervene every time the guest edits its page tables. Translating every access in software would be far too slow.

  • A. The hypervisor's tables are used too, in a two-stage translation.
  • B. Correct. Guest virtual → guest physical → host physical, in two stages.
  • C. Translating everything in software would be far too slow.
Practice this topic Back to topic

More OS & Hardware questions

  1. In nested paging where both guest and host use 4-level page tables, how many memory accesses can a TLB miss require in the worst case?
  2. What is it called when a guest OS executes a privileged instruction, control passes to the hypervisor, and the hypervisor reproduces the instruction's effect on its behalf?
  3. Which describes paravirtualization?
  4. Which correctly distinguishes containers from virtual machines?
  5. Many OSes map the kernel into part of every process's address space (for example the upper range) and forbid user-mode access through page-table protection bits. What is the main advantage of this layout?